Fault-tolerant analysis and algorithms for a proposed augmented binary tree architecture

In this paper an "Augmented Binary Tree" architecture is proposed with a view to provide faulttolerance. This architecture is an augmentation of an n-level full binary tree with n redundant nodes and 2+3n-6 redundant links. The AB-tree can be configured into a full binary tree even when one node is faulty at each level. While functionally equivalent to the RAE-tree [13], the proposed AB-tree has a regular topology, reduced number of maximum input-output channels per processor, and fewer number of wire crossovers in VLSI layout. A reconfiguration algorithm, which constructs an nlevel full binary tree from an n-level faulty ABtree, is given. A distributed fault diagnosis algorithm, that runs concurrently on each nonfaulty processor, enables each nonfaulty processor to identify all faulty processors, is also given.